Abstract:

Hardware security has recently taken the center stage even in informative articles for the public and other media, after being relegated to the scientific literature for various years. The concerning implications of attacks to confidential user data have recently made HW security an important differentiator in commercial chips, and is fueling a vigorous and global research effort to make chips more secure.

HW security is now being demanded in energy-constrained integrated systems (e.g., sensor nodes, wearables, biomedical), in view of their pervasiveness and connectivity. This has spurred the requirement of low-overhead low-energy solutions that allow security to be rooted in hardware, as opposed to more traditional and expensive techniques that can be amortized in highly-complex Systems on a Chip (e.g., cutting-edge microprocessors). This poses a new set of challenges that need a fundamental rethinking of silicon solutions for security, from the root of trust to security assurance across the entire chain of trust.

In this tutorial, the principles and the available state-of-the-art techniques for hardware security are discussed from the perspective of energy-constrained systems. The fundamentals are systematically exemplified with cutting-edge circuit and architectural approaches, including silicon demonstrations from industry and academia (including our group’s work). A framework to link up applications to circuit requirements is introduced, providing an insight into how to achieve such requirements. Techniques to create on-chip security primitives for root/chain of trust are discussed, from static (e.g., PUFs) to dynamic entropy generation (e.g., TRNGs), lightweight ciphers and hashing. Then, techniques and innovative approaches to protect chips against hardware and physical attacks are reviewed, and exemplified with experimental results. Emphasis is given on low-cost techniques for security down to low-end devices, for pervasive adoption.

At the end of the tutorial, the attendees will have a solid understanding of the basic principles of hardware security, its state of the art, and what challenges lie beyond the current frontier.

Biographies

• Massimo Alioto

  (M'01–SM'07-F'16) received the Laurea (MSc) degree in Electronics Engineering and the Ph.D. degree in Electrical Engineering from the University of Catania (Italy) in 1997 and 2001, respectively. He is with the Department of Electrical and Computer Engineering, National University of Singapore where he leads the Green IC group and is the Director of the Integrated Circuits and Embedded Systems area. Previously, he held positions at the University of Siena, Intel Labs – CRL (2013), University of Michigan Ann Arbor (2011-2012), BWRC – University of California, Berkeley (2009-2011), and EPFL (Switzerland, 2007).

  He has authored or co-authored more than 250 publications on journals and conference proceedings. He is co-author of three books, including the first book on integrated circuit and system design for the IoT (Enabling the Internet of Things - from Circuits to Systems, Springer, 2017). His primary research interests include ultra-low power and self-powered systems, near-threshold and widely-voltage scalable circuits, energy-quality scalable integrated systems, data-driven integrated systems and embedded machine learning, hardware-level security, among the others.

  He is the Editor in Chief of the IEEE Transactions on VLSI Systems (2019-2020), and the Deputy Editor in Chief of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2018). He served as Guest Editor of several IEEE journal special issues (TCAS-I, TCAS-II, JETCAS), and as Associate Editor of a number of IEEE and ACM journals. Prof. Alioto is/was Technical Program Chair (ISCAS 2022, SOCC, ICECS, NEWCAS, VARI, ICM, PRIME), Track Chair in numerous conferences (ICCD, ISCAS, ICECS, VLSI-SoC, APCCAS, ICM), and TPC member of others (ISSCC, ASSCC). Prof. Alioto is an IEEE Fellow.